1. Field of the Invention
The present invention relates generally to packaging substrates, and, more particularly, to a coreless packaging substrate and a method of fabricating the same.
2. Description of Related Art
With the rapid development of electronic industry, electronic products are trending toward multi-function and high-performance. Currently, the semiconductor package structure has developed various package types such as wire bonding or flip chip that forms a semiconductor chip on a packaging substrate, and the semiconductor chip electrically connects to the packaging substrate by bonding wires or solder bumps. In order to meet the packaging requirements of high integration and miniaturization for semiconductor packages, and to provide a packaging substrate that allows more active and passive components and circuits to be installed and formed thereon, a multi-layer substrate is developed to replace a dual-layer board gradually, so as to use an interlayer connection technique under limited space for enhancing the available layout area on the packaging substrate, such that the requirement of highly integrated circuit can be met with a reduced thickness of the packaging substrate, and that the purpose of improving electrical function is achieved with a compact package structure.
A packaging substrate of the prior art comprises a core board having inner circuits and two circuit buildup structures symmetrically installed on two surfaces of the core board. The use of the core board causes the overall structure to have an increased thickness, which is contradictory to the requirements of increasing performance and reducing sizes.
A packaging substrate that has a coreless structure comes to the market, in order to satisfy the demands of shortened conductive length and reduced structure thickness. As shown in FIG. 1, a method of fabricating a coreless packaging substrate 1 includes forming a first dielectric layer 10 on a carrier board (not shown); forming a first wiring layer 11 having a plurality of first electrical pads 110 on the first dielectric layer 10; forming a circuit buildup structure 12 on the first dielectric layer 10 and the first wiring layer 11, the circuit buildup structure 12 having at least a second dielectric layer 120; forming a second wiring layer 121 on the second dielectric layer 120; electrically connecting the first and second wiring layers 11 and 121 by a plurality of conductive vias 122, the uppermost one of the second wiring layers 121 having a plurality of second electrical pads 123; removing the carrier board to expose the first dielectric layer 10; forming solder masks 14a and 14b on the first dielectric layer 10, the uppermost one of the second dielectric layers 120, and the second wiring layer 121; forming a plurality of openings 140a and 140b on the solder masks 14a and 14b and the first dielectric layer 10 corresponding to the exposed part of the top surface of each of the first and second electrical pads 110 and 123; and forming metal bumps 13a and 13b in the openings 140a and 140b for connecting the solder balls 15a and 15b, such that the upper side solder balls 15b electrically connect the solder bumps (not shown) of the chip and the lower side solder balls 15a electrically connect the circuit board (not shown).
Although it is necessary in the conventional packaging substrate 1 to form the openings 140a and 140b on the solder masks 14a and 14b, the alignment between the solder balls 15a and 15b and the openings 140a and 140b is not easy, thus increasing the difficulty of the process.
Furthermore, the openings 140b of the solder mask 14b only expose a part of the top surface of each of the second electrical pads 123, rather than the entire top surface, so that the area of the top surface of each of the metal bumps 13b is reduced, resulting in weakening of the bonding force between the metal bumps 13b and the chip at the time the chip is installed on the packaging substrate 1, thereby making the chips easily fallen off from the packaging substrate 1 and damaged.
Also, in order to avoid short-circuit resulting from the bridging between the upper side solder balls 15b, and to consider the size of each of the openings 140b of the solder mask 14b for maintaining the bonding force between the metal bumps 13b and the solder mask 14b, the distance between any two neighboring ones of the second electrical pads 123 needs to be increased, so that the spacing between any two neighboring ones of the second electrical pads 123 can not meet fine pitching requirement, resulting in difficulty to improve the layout density of the second electrical pads 123.
Therefore, it is imperative to overcome the above drawbacks of the prior art.